ss569 hall latch - high sensitivity packages features and benefits ? wide operating voltage range from 2.5v to 24v ? high magnetic sensitivity ? multi-purpose ? cmos technology ? low current consumption ? chopper-stabilized amplifier stage ? output driver with internal pull-up resistor ? superior temperature stability ? insensitive to physical stress ? tiny sot23 3l or flat sip 3l 3 pin sot23 (suffix so) 3 pin sip (suffix ua) both rohs compliant packages ? functional block diagram application examples ? automotive, consumer and industrial ? solid-state switch ? brushless dc motor commutation ? speed detection ? angular position detection ? linear position detection ? proximity detection ? general description the ss569 is a bipolar hall effect sensor ic fabricated from mixed signal cmos technology. the device integrates a voltage regulator, hall sensor with dynamic offset cancellation system, schmitt trigger and an output driver with internal pull-up resistor, all in a single package. it incorporates advanced chopper stabilization techniques to provide accurate and stable magnetic switch points. there are many applications for this hed ? hall electronic device - in addition to those listed above. the design, specifications and performance have been optimized for commutation applications in 5v and 12v brushless dc motors. thanks to its wide operating voltage range and extended c hoice of temperature range, it is quite suitable for use in automotive, industrial and consumer applications. the device is delivered in a small outline transistor (sot) for surface mount process or in a plastic single in line (sip 3l flat) for through- hole mount. both 3-lead packages are rohs compliant. vdd out voltage regulator choppe r hall plate gnd sip package sot package pin 1 ? v dd pin 1 ? v dd pin 2 ? gnd pin 2 ? out pin 3 ? out pin 3 ? gnd ? 1 v2.10 may 1, 2012
ss569 hall latch - high sensitivity glossary of terms millitesla (mt), gauss units of magnetic flux density: 1mt = 10 gauss rohs restriction of hazardous substances sot small outline transistor (sot package) - also referred with the package code ?so? esd electro-static discharge bldc brush-less direct-current operating point (b op ) magnetic flux density applied on the branded side of the package which turns the output driver on (v out = v dson ) release point (b rp ) magnetic flux density applied on the branded side of the package which turns the output driver off (v out = high) unique features based on mixed signal cmos technology, ss569 is a hall-effect device with high magnetic sensitivity. this multi-purpose latch meets most of the application requirements. the chopper-stabilized amplifier uses switched capacitor tec hnique to suppress the offset generally observed with hall sensors and amplifiers. the cmos technology makes this advanced technique possible and contributes to smaller chip size and lower current consumption than bipolar technology. the small chip size is also an important factor to minimize the effect of physical stress. this combination re sults in more stable magnetic characteristics and enables faster and more precise design. the wide operating voltage from 2.5v to 24v, low current consumption and large choice of operating temperature range according to ?l?, and ?e? specification make this device suitable for automotive, industrial and consumer applications. pin definitions and descriptions ? sot pin sip pin name type function 1 1 vdd supply supply voltage pin 2 3 out output open drain output pin 3 2 gnd ground ground pin table 1: pin definitions and descriptions 2 v2.10 may 1, 2012
ss569 hall latch - high sensitivity absolute maximum ratings parameter symbol value units supply voltage v dd 28 v supply current i dd 50 ma output voltage v out 28 v output current i out 50 ma storage temperature range t s -50 to 150 c maximum junction temperature t j 165 c table 2: absolute maximum ratings operating temperature range symbol value units temperature suffix ?e? t a -40 to 85 c temperature suffix ?l? t a -40 to 150 c exceeding the absolute maximum ratings may cause perm anent damage. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. general electrical specifications dc operating parameters t a = 25 , v dd = 2.5v to 24v (unless otherwise specified) parameter symbol test conditions min typ max units supply voltage v dd operating 2.2 24 v supply current i dd b < b rp 5 ma output saturation voltage v dson i out = 20ma, b > b op 0.5 v output leakage current i off b < b rp v out = 24v 1 10 a output rise time t r r l = 1k ? , c l = 20pf 0.25 s output fall time t f r l = 1k ? , c l = 20pf 0.25 s internal pull-up resistor rpu --- 9 12 15 k ? maximum switching frequency f sw --- 10 khz package thermal resistance r th single layer (1s) jedec board 301 c/w table 3: electrical specifications note : the output of ss569 will be switched after the supply voltage is over 2.2v, but the magnetic characteristics won't be normal until the supply is over 2.5v. output behavior versus magnetic pole dc operating parameters t a = -40 to 150 , v dd = 2.5v to 24v (unless otherwise specified) parameter test conditions (so) out (so) test conditions (ua) out (ua) south pole b < b rp high b > b op low north pole b > b op low b < b rp high table 4: output behavior versus magnetic pole 3 v2.10 may 1, 2012
ss569 hall latch - high sensitivity magnetic specifications dc operating parameters v dd = 2.5v to 24v (unless otherwise specified) ss569 parameter symbol test conditions min typ max units operating point b op 10 18 30 g release point b rp -30 -18 -10 g hysteresis b hyst e spec., t a = 85c 36 g operating point b op 8 18 35 g release point b rp -35 -18 -8 g hysteresis b hyst e spec., t a = 85c 36 g operating point b op 5 18 40 g release point b rp -40 -18 -5 g hysteresis b hyst l spec., t a = 150c 36 g table 4: magnetic specifications detailed general description the ss569 exhibits latch magnetic switching characteristics. therefore, it requires both south and north poles to operate properly. the out pin of these devices switches low (turns on) when a magnetic field perpendicular to the hall sensor exceeds the operate point threshold, b op . after turn-on, the output voltage is v dson . note that the device latches, that is, a south pole of sufficient strength towards the branded surface of the device turns the device on. the device remains on if the south pole is removed (b 0). this latching property defines the device as a magnetic memory. when the magnetic field is reduced below the release point, b rp , the out pin turns off (goes high). the difference in the magnetic operating and release points is the hysteresis, b hyst , of the device. this built-in hysteresis prevents output oscillation near the switching point, and allows clean sw itching of the output even in the presence of external mechanical vibration and electrical noise. the device behaves as a latch with symmetric operating and release switching points (b op =|b rp |). this means magnetic fields with equivalent strength and opposite direction drive the output high and low. powering-on the device in the hysteresis region (less than b op and higher than b rp ) allows an indeterminate output state. the correct state is attained after the first excursion beyond b op or b rp . the sot-23 device is reversed from the ua package. the sot- 23 output transistor will be latched on in the presence of a sufficiently strong north pole magnetic field applied to the marked face. out p ut level out p ut level 4 v2.10 may 1, 2012 0mt 0mt out = high out = high flux densit y b op 18gs typ out = low out = low ua package - latch characteristic b op 18gs typ b rp -18gs typ b rp -18gs typ flux densit y so package - latch characteristic ? hyst b b hyst
ss569 hall latch - high sensitivity application information it is strongly recommended that an external bypass capac itor be connected (in close proximity to the hall sensor) between the supply (vdd pin) and ground (gnd pin) of the de vice to reduce both external noise and noise generated by the chopper stabilization technique. as is s hown in the two figures in next page, a 0.1 f capacitor is typical. for reverse voltage protection, it is r ecommended to connect a resistor or a di ode in series with the vdd pin. when using a resistor, three points are important: - the resistor has to limit the reverse current to 50ma maximum (v cc / r1 50ma) - the resulting device supply voltage v dd has to be higher than v dd min (v dd = v cc ? r1*i dd ) - the resistor has to withstand the power dissipated in reverse voltage condition (p d = v cc 2 /r1) when using a diode, a reverse current cannot flow and the voltage drop is almost constant ( 0.7v). therefore, a 100 ? /0.25w resistor for 5v application and a diode for higher supply voltage are recommended. both solutions provide the required reverse voltage protection. when a weak power supply is used or wh en the device is intended to be used in noisy environment, it is recommended that the figure 13.3 from the application information section is used. the low-pass filter formed by r1 and c1 and the zener diode z1 bypass the disturbances or voltage spikes occurring on the device supply voltage v dd . the diode d1 provides additional reverse voltage protection. the ss569 have been optimized for commutation applications in 5v and 12v brushless dc motors. the follow figure is the typical application circuit for 3 phase brushless dc motors. 5 v2.10 may 1, 2012 ss569 r2 c2 vdd gnd out c1 ss569 r1:100 r2 c2 automotive and severe environment protection circuit typical three-wire application circuit z1 d1 c1 gnd out vdd
ss569 hall latch - high sensitivity standard information regarding ma nufacturability of hall ic with different soldering processes our products are classified and qualified regarding solderi ng technology, solderability and moisture sensitivity level according to following test methods: reflow soldering smd?s (surface mount devices) ? ipc/jedec j-std-020 moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices (classification reflow profiles according to table 5-2) ? eia/jedec jesd22-a113 preconditioning of nonhermetic surface mount devices prior to reliability testing (reflow profiles according to table 2) wave soldering smd?s (surface mount devices) and thd?s (through hole devices) ? en60749-20 resistance of plastic- encapsulated smd?s to comb ined effect of moisture and soldering heat ? eia/jedec jesd22-b106 and en60749-15 resistance to soldering temperature for through-hole mounted devices iron soldering thd?s (through hole devices) ? en60749-15 resistance to soldering temperature for through-hole mounted devices solderability smd?s (surface mount devices ) and thd?s (through hole devices) ? eia/jedec jesd22-b102 and en60749-21 solderability esd precautions electronic semiconductor products are sensitive to electro static discharge (esd). always observe electro static discharge control pr ocedures whenever handling semiconductor products. package ua, 3-pin sip: 6 v2.10 may 1, 2012
ss569 hall latch - high sensitivity ? 7 v2.10 may 1, 2012
ss569 hall latch - high sensitivity package sot, 3-pin sot-23: sot-23 package hall location: ? ordering information part no. pb-free temperature code package code packing ss569esot yes -40c to 85c sot-23 7-in. reel, 3000 pieces/reel SS569EUA yes -40c to 85c to-92 bulk, 1000 pieces/bag ss569ksot yes -40c to 125c sot-23 7-in. reel, 3000 pieces/reel ss569kua yes -40c to 125c to-92 bulk, 1000 pieces/bag ss569lsot yes -40c to 150c sot-23 7-in. reel, 3000 pieces/reel ss569lua yes -40c to 150c to-92 bulk, 1000 pieces/bag ? 8 v2.10 may 1, 2012
|
